A cell for a static random access memory (SRAM) is characterized by operation in one of two mutually exclusive and cell-maintaining operating states. Each operating state defines one of the two possible binary bit values, zero or one. A static memory cell typically has an output which reflects the operating state of the memory cell. Such an output produces a "high" voltage to indicate a "set" operating state. The memory cell output produces a "low" voltage to indicate a "reset" memory cell operating state. A low or reset output voltage usually represents a binary value of zero, and a high or set output voltage represents a binary value of one.
A static memory cell is said to be bi-stable because it has two stable or self-maintaining operating states, corresponding to two different output voltages. Without external stimuli, a static memory cell will operate continuously in a single one of its two operating states. It has internal feedback to maintain a stable output voltage, corresponding to the operating state of the memory cell, as long as the memory cell receives power.
The operation of a static memory cell is in contrast to other types of memory cells, such as for dynamic random access memory (DRAM), which do not have stable operating states. A dynamic memory cell can be programmed to store a voltage which represents one of two binary values, but requires periodic reprogramming or "refreshing" to maintain this voltage for more than a few milliseconds. A dynamic memory cell has no feedback to maintain a stable output voltage. Without refreshing, the output of a dynamic memory cell will drift toward intermediate or indeterminate voltages, effectively resulting in loss of data.
Dynamic memory cells are used in spite of this limitation because of the significantly greater packaging densities which can be attained. For instance, a dynamic memory cell can be fabricated with a single MOSFET transistor, rather than the six transistors typically required in a static memory cell. Because of the significantly different architectural arrangements and functional requirements of static and dynamic memory cells and circuits, static memory design has developed along a different path than has the design of dynamic memories.
Ongoing efforts in SRAM circuitry to improve active loads has brought about the development of thin film transistors and inverted TFTs in attempts to provide low leakage current as well as high noise immunity. A process for forming an inverted TFT design is shown in FIGS. 1-3. As shown in FIG. 1, a wafer substrate 10, usually silicon, has a layer of dielectric 12, usually an oxide, and a patterned gate region 14, usually doped polycrystalline silicon (poly), formed thereupon. A second dielectric layer 16 isolates the gate region 14 from a second poly layer 18. The wafer surface is then doped, for example with an N-type dopant such as phosphorous, to result in an N-type poly layer 18.
As shown in FIG. 2, a mask 20, such as a resist, is patterned over the gate region 14 and poly layer 18 is again doped, for example with a P-type dopant such as boron, thereby lightly counterdoping the exposed poly regions 22 while leaving the poly regions 24 covered by the mask 20 N-type.
Referring to FIG. 3, a second mask 30 is patterned over a portion of the gate region 14, and the wafer surface is positively doped a second time, thereby resulting in the second poly layer having three differentially doped regions, highly doped P-type regions 32, lightly doped P-type regions 34, and an N-type region 36. Region 34a will form a transistor source LDD, and 34b will form a transistor drain LDD, while region 36 will provide a transistor channel region for the gate 14.
This process can have misalignment problems as it requires two masks, and therefore two patterning steps. If mask 20 or mask 30 is misaligned to the gate 14, the lightly doped source-drain regions can be misaligned, thereby creating a transistor having unfavorable electrical properties and lower yields. A need remains for a TFT formation process which has reduced problems of misalignment.